Dual write cycle programmable conductor memory system and method of operation

ABSTRACT

The present invention provides a method and apparatus for writing a programmable conductor random access memory (PCRAM) element. After a read operation of the memory element a complement logical state from that read is written back to the memory element. In one embodiment the memory element is then again written back to its original state. In another embodiment logic circuitry keeps track of whether the original logic state or its complement are stored in the memory element so that during the next read the stored logic will be correctly read.

FIELD OF INVENTION

[0001] The present invention relates to integrated memory circuits. Morespecifically, it relates to a method for writing a programmableconductor random access memory (PCRAM) cell.

BACKGROUND OF THE INVENTION

[0002] Dynamic random access memory (DRAM) integrated circuit arrayshave existed for more than thirty years and their dramatic increase instorage capacity has been achieved through advances in semiconductorfabrication technology and circuit design technology. The tremendousadvances in these two technologies have also achieved higher levels ofintegration that permit dramatic reductions in memory array size andcost, as well as increased process yield.

[0003]FIG. 1 is a schematic diagram of a DRAM memory cell 100 comprisingan access transistor 101 and a capacitor 102. The capacitor 102, whichis coupled to a Vcc/2 potential source and the transistor 101, storesone bit of data in the form of a charge. Typically, a charge of onepolarity (e.g., a charge corresponding to a potential difference acrossthe capacitor 102 of +Vcc/2) is stored in the capacitor 102 to representa binary “1” while a charge of the opposite polarity (e.g., a chargecorresponding to a potential difference across the capacitor 102 of−Vcc/2) represents a binary “0.” The gate of the transistor 101 iscoupled to a word line 103, thereby permitting the word line 103 tocontrol whether the capacitor 102 is conductively coupled via thetransistor 101 to a bit line 104. The default state of each word line103 is at ground potential, which causes the transistor 101 to beswitched off, thereby electrically isolating capacitor 102.

[0004] One of the drawbacks associated with DRAM cells 100 is that thecharge on the capacitor 102 may naturally decay over time, even if thecapacitor 102 remains electrically isolated. Thus, DRAM cells 100require periodic refreshing. Additionally, as discussed below,refreshing is also required after a memory cell 100 has been accessed,for example, as part of a read operation.

[0005] Efforts continue to identify other forms of memory elements forus in memory cells, particularly for memory elements which do notrequired frequent refresh operations. Recent studies have focused onresistive materials that can be programmed to exhibit either high or lowstable ohmic states. A programmable resistance element of such materialcould be programmed (set) to a high resistive state to store, forexample, a binary “1” data bit or programmed (set) to a low resistivestate to store a binary “0,” data bit. The stored data bit could then beread by detecting the magnitude of a readout current switched throughthe resistive memory element by an access device, thus indicating itsprogrammed stable resistance state.

[0006] Recently programmable conductor materials, such as chalcogenideglasses, have been investigated as data storage memory cells for use inmemory devices. U.S. Pat. Nos. 5,761,115, 5,896,312, 5,914,893, and6,084,796 all describe chalcogenide glass materials which can be used asprogrammable conductor memory elements and are incorporated herein byreference. One characteristic of such an element is that it typicallyincludes a chalcogenide glass which is doped with metal ion and acathode and anode spaced apart on a surface of the glass. Application ofa voltage across the cathode and anode causes the glass to achieve a lowresistance state. One theory for this is that the applied voltage causesgrowth of a nearly non-volatile metal dendrite in or on the surface ofthe glass which changes the resistance and capacitance of the memoryelement which can then be used to store data.

[0007] One particularly promising programmable conductor material is achalcogenide glass formed as an alloy system including Ge:Se:Ag forexample, a Ge_(x):Se_((1−x)) composition which is doped with silver. Amemory element comprised of a chalcogenide glass has a natural stablehigh resistive state but can be programmed to a low resistance state bypassing a current pulse from a voltage of suitable polarity through thecell. A chalcogenide memory element is simply written over by theappropriate current pulse and voltage polarity (reverse of that whichwrites the cell to a low resistance state) to reprogram it, and thusdoes not need to be erased. Moreover, a memory element of chalcogenidematerial is nearly nonvolatile, in that it need only be rarely refreshedin order to retain its programmed low resistance state. Such memorycells, unlike DRAM cells, can be accessed without requiring a refresh.

[0008] Since there is a considerable body of known and proven circuitryfor reading, writing and refreshing DRAM memory cells, it would bedesirable to use the same or similar circuitry with programmableconductor memory elements. However, while conventional read senseamplifier circuitry, associated with DRAM cells, are capable of use inaccessing and sensing programmable element random access memory (PCRAM)cells, the natural refresh operation associated with these senseamplifiers is not required for a programmable conductor memory element.Indeed, frequent rewriting of PCRAM memory elements to the same state isnot desirable because it can cause the memory element to wear outfaster. Accordingly, there is a need and desire for a circuit and methodfor writing PCRAM cells without causing premature deterioration.

SUMMARY OF THE INVENTION

[0009] The present invention provides an improved method for reading aprogrammable conductor memory element which reduces prematuredeterioration due to repeated refresh operations. This is accomplishedby first performing a read operation on a memory element and thenwriting the memory element to the opposite or complement logical statefrom the state which was read and then writing the memory element backto the original logical state. Hence, if following a high resistancestate read operation the memory element is to be written to a highresistance state, then the memory element is first written to theopposite state (i.e., low resistance state) and then written back to theoriginal state (i.e., high resistance state). Alternatively, iffollowing a low resistance state read operation the PCRAM cells are tobe written to a low resistance state, then the cells are first writtento the opposite state (i.e., high resistance state) and then writtenback to the original state (i.e., low resistance state).

[0010] In an alternative embodiment, after a read operation the memoryelement may simply be re-written to a state complementary to the readstate and logic circuitry associated with a memory device containing thememory element keeps track during a read operation if the read datashould output as read or after being inverted. For example, if a highresistance state represents a “1” data value and a low resistance staterepresents a “0” data value, and if a memory element is read as a “1”that memory element will be written to a “0” state following the readoperation. During a subsequent read of the same memory element, as a “0”the logic circuitry will invert the logic state and output it correctlyas a “1.” After the subsequent read, the memory element will then bewritten to a “1” state and the logic circuit will note that no logicalstate inversion is required for the next read of the memory element.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The foregoing and other advantages and features of the inventionwill become more apparent from the detailed description of exemplaryembodiments of the invention given below with reference to theaccompanying drawings in which:

[0012]FIG. 1 is a schematic diagram of a conventional DRAM cell;

[0013]FIG. 2 is a schematic diagram of a PCRAM cell;

[0014]FIG. 3 is a schematic diagram a PCRAM array;

[0015]FIGS. 4A and 4B are timing diagrams illustrating the voltages onthe word and bit lines when a PCRAM cell is read in high resistance andlow resistance states, respectively;

[0016]FIG. 5 is a schematic diagram of a sense amplifier used in theinvention;

[0017]FIG. 6 depicts a flowchart describing an operational flow, inaccordance with an exemplary embodiment of the invention;

[0018]FIG. 7 depicts a voltage arrangement across the PCRAM memory cellof FIG. 2;

[0019]FIG. 8 is a schematic diagram of a portion of the FIG. 3 circuitwith added refresh circuitry; and

[0020]FIG. 9 is a block diagram of a processor based system including aPCRAM memory device in accordance with the principles of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0021] Referring to the drawings, where like reference numeralsdesignate like elements, FIG. 2 illustrates a PCRAM cell 400 and in FIG.3 a memory device 500 comprised of a plurality of PCRAM cells 400 a-400h. As illustrated in FIG. 2, a PCRAM cell 400 comprises an accesstransistor 401, a programmable conductor memory element 402, and acommon cell plate 403 for a plurality of cells. The access transistor401 has its gate coupled to a word line 405 and one terminal coupled toa bit line 406. A small portion of an array of such cells is shown inFIG. 3 as including bit lines 406 a, 406 a′, 406 b, 406 b′, and wordlines 405 a, 405 b, 405 c, and 405 d. As shown in FIG. 3, the bit lines406 a, 406 a′, and 406 b, 406 b′ are coupled to respective pre-chargecircuits 501 a, 501 b, which can switchably supply a pre-chargepotential to the bit lines 406 a, 406 a′, 406 b, 406 b′. The otherterminal of each access transistor 401 is coupled to one end of anassociated programmable conductor memory element 402, while the otherend of the associated programmable conductor memory element 402 iscoupled to the cell plate 403. The cell plate 403 may span and becoupled to several other PCRAM cells. The cell plate 403 is also coupledto a potential source. In the exemplary embodiment the potential sourceis at (Vdd/2).

[0022] The access transistor 401, as well as the other accesstransistors, are depicted as N-type CMOS transistors, however, it shouldbe understood that P-type CMOS transistors may be used as long as thecorresponding polarities of the other components and voltages aremodified accordingly. The programmable conductor memory element 402 ispreferably made of chalcogenide glass having a Ge_(x):Se:_((1−x))composition (e.g., x=0.2 to 0.3) which is doped with silver, however, itshould be understood that any other bi-stable programmable conductormaterial known to those with ordinary skill in the art may also be used.In the exemplary embodiment of a Ge_(x):Se:_((1−x)) glass where x=0.2 to0.3, the programmable conductor memory element 402 stores a binary “0”state when it has a resistance of approximately 10 K ohm, and a binary“1” when it has a resistance greater than 10 M ohm. The programmableconductor memory element is normally at rest in a high resistive statebut can be programmed to a low resistance state, e.g., binary “0” state,by applying a voltage greater than or equal to approximately +0.25 voltacross the memory element. A memory element programmed to a lowresistance state can be programmed to a high resistance value, e.g., abinary “1” state, by applying a voltage greater than or equal toapproximately −0.25 volt across the memory element. The programmableconductor can be nondestructively read by applying a reading voltagehaving a magnitude of less than 0.25 volt across the memory element. Inthe exemplary embodiment, the reading voltage of approximately 0.2 voltcan be used. However, it should be readily apparent that other alternatevoltages may be selected as required for programmable conductor memoryelements formed of the indicated or other material compositions.

[0023]FIG. 3 illustrates a memory device 500 comprising a pair of memoryarrays 550 a, 550 b. Each memory array 550 a, 550 b includes a pluralityof memory cells 400 a-400 d, 400 e-400 h arranged such that the memorycells 400 along any given bit line 406 a, 406 a′, 406 b, 406 b′ do notshare a common word line 405 a-405 d. Conversely, the memory cells 400along any word line 405 a-405 d do not share a common bit line 406 a,406 a′, 406 b, 406 b′. A selected word line is switchably coupled to anassociated word line driver 512 a-512 d via a transistor 510 a-510 d inaccordance with the output of a row decoder. A bit line 406 a, 406 a′,406 b, 406 b′ is selected for use in accordance with the output of acolumn decoder. Each memory array 550 a, 550 b has its own set of bitlines. For example, memory array 550 a includes bit lines 406 a, 406 b,while memory array 550 b includes bit lines 406 a′, 406 b′. The bitlines from each adjacent pair of memory arrays 550 a, 550 b are coupledto a common sense amplifier 300 a, 300 b. For example, bit lines 406 a,406 a′ are coupled to sense amplifier 300 a, while bit lines 406 b, 406b′ are coupled to sense amplifier 300 b. For simplicity, FIG. 5illustrates a memory device having only two arrays 550 a, 550 b, andeight cells 400 a-400 h. However, it should be understood that theillustrated memory device would typically have significantly more cellsand arrays.

[0024] The memory device 500 also includes a plurality of pre-chargecircuits 501 a-501 b. One pre-charge circuit (e.g., 501 a) is shown asbeing provided for each pair of bit lines coupled to a sense amplifier(e.g., 406 a, 406 a′), however, other pre-charge arrangements are alsopossible. Each pre-charge circuit (e.g., 501 a) includes two transistors(e.g., 502 a, 502 b). One terminal of each transistor is coupled to apotential source Vdd. In the exemplary embodiment, the potential sourceVdd is 2.5 volts. Another terminal of each transistor (e.g., 502 a, 502b) is coupled to its corresponding bit line (e.g., 406 a, 406 a′,respectively). The gate of the each transistor (e.g., 502 a, 502 b) iscoupled to a pre-charge control signal. As illustrated, the transistors(e.g., 502 a, 502 b) are P-MOS type transistor. Thus, when thepre-charge signal is low, the transistors (e.g., 502 a, 502 b) conduct,thereby pre-charging the bit lines (e.g., 406 a, 406 a′). When thepre-charge signal is high, the transistors (e.g., 502 a, 502 b) areswitched off Due to capacitance inherent in the bit lines (e.g., 406 a,406 a′), the bit lines will hold the pre-charge voltage level of 2.5volts for a period of time.

[0025] Reading a PCRAM cell, for example, cell 400 a, in the PCRAMdevice 500 comprises the operations of accessing a memory element andsensing/refreshing the memory element.

[0026] During a read operation a small potential difference is createdbetween the bit lines (e.g., 406 a, 406 a′) coupled to the same senseamplifier (e.g., 300 a) for a memory cell e.g., a 400 a, being read. Oneof the bit lines, e.g. 406 a maintains an applied pre-charge voltage asa reference for the sense amplifier 300 a, while the other bit line e.g.406 a′ starts with a voltage slightly higher than the pre-charge voltagedue to parasitic capacitance between that bit line and an associated rowline of the cell 400 being read, e.g. 400 a. During a read operation fore.g. cell 400 a, the voltage on bit line 406 a is discharged throughmemory element e.g. 402 a. This small potential difference between thereference voltage and the discharging voltage on bit line 406 a can besensed by sense amplifier 300 a to determine the resistance and logicalstate of memory element 400 a.

[0027] Now also referring to FIG. 6, the read operation begins with thepre-charging of the bit lines 406 a, 406 a′, 406 b, 406 b′ of the memorydevice 500 via pre-charge circuits 501 a-501 b (step S1). The bit linesmay be pre-charged by temporarily bringing the pre-charge signal low,causing transistors 502 a-502 d to conduct the pre-charge voltage (Vdd)to the bit lines 406 a, 406 a′, 406 b, 406 b′. Once the pre-chargesignal returns to a high state, the transistors 502 a-502 d stopconducting, but the bit lines 406 a, 406 a′, 406 b, 406 b′ will remainat the pre-charge potential for a predetermined period due to thecapacitance inherent in the bit lines. The precharge period isillustrated as the time prior to T1 in FIGS. 4A, 4B.

[0028] In the exemplary embodiment, a selected pair of bit lines e.g.406 a, 406 a′, are pre-charged to 2.5 volts and the cell plate 403 a,403 b is tied to 1.25 volts (Vdd/2). However, the pre-charge voltage inbit line 406 a is slightly higher as noted, e.g. to 2.6 volts when rowline 405 a is activated. When the row line is activated at time T1(FIGS. 4A, 4B), e.g. row line 405 a, there is a voltage drop across theaccess transistor, e.g. 401 a, which causes a voltage of approximately0.2 volts to appear across the memory element 402 a. The potentialdifference between the bit line 406 a and the cell plate 403 a willcause the bit line to discharge to the cell plate through the conductingaccess transistor 401 and the programmable conductor memory element 402a. The discharge rate is dependent upon the resistive state of theprogrammable conductor memory element 402. That is, a low resistivestate will cause the voltage on selected bit line 406 a to dischargefaster than a high resistive state. As the bit line discharges, itsvoltage will fall from the original voltage of approximately 2.6 voltstoward the cell plate voltage.

[0029] In the memory device 500, the word lines 405 a-405 d are normallyat ground potential. Thus the access transistors 401 a-401 d arenormally switched off. Referring now to FIGS. 4A and 4B, at time T1, theword line 405 a associated with a cell 400 a to be read is activated bybringing its potential from ground to a predetermined level (step S2 inFIG. 6). The predetermined level is designed to create a reading voltageat the programmable element 402 a, which as previously explained, musthave a magnitude less than the magnitude of a writing voltage. In theexemplary embodiment, the word line 405 a is brought to approximately2.25 volts. Since the voltage drop across the transistor 401 a isapproximately 1.15 volts, the potential at the interface between thetransistor 401 a and the programmable element 402 a is 1.45 volt. Thisresults in a reading voltage of 0.2 volt across the programmable memoryelement 402 a since the voltage at the interface between theprogrammable element 402 a and the cell plate 403 a is maintained at1.25 volt.

[0030] As noted, due to the inherent parasitic capacitance between theword line 401 a and its associated bit lines 406 a the potential in theassociated bit line 406 a increase as the word line 401 a is activated.In the exemplary embodiment, the potential in bit line 406 a increasesby 0.1 volt to 2.6 volt. It should be noted that the word lines 405 c,405 d coupled to complementary bit lines 406 a′, 406 b′ remain at groundpotential. Thus, bit lines 406 a′, 406 b′ remain at the pre-chargepotential, which is 2.5 volt in the exemplary embodiment.

[0031] The increased potential of bit line 406 a is used in combinationwith the two bi-stable resistive states of the programmable element 402a to cause one of the bit lines (e.g., 406 a) coupled to a senseamplifier (e.g., 300 a) to have either a greater or lesser voltage thanthe other bit line (e.g., 406 a′) coupled to the same sense amplifier300 a. The memory is designed and operated so that if the programmableelement 402 a has a high resistive state, bit line 406 a discharges moreslowly, thereby causing it to maintain its relatively higher potential.However, if the programmable element 402 a has a low resistive state,bit line 406 a discharges at a faster rate, so that bit line 406transitions to a lower potential state than bit line 406 a′. These twoeffects can be seen by comparing FIG. 4A (illustrating the effects of aprogrammable element at a high resistive state) and FIG. 4B(illustrating the effects of a programmable element at a low resistivestate.)

[0032]FIG. 5 is detailed illustration of a sense amplifier 300, whichcomprises a N-sense amp 310N and a P-sense amp portion 310P. The N-senseamp 310N and the P-sense amp 310P include nodes NLAT* and ACT,respectively. These nodes are coupled to controllable potential sources(not illustrated) which supply control signals which respectively turnon the N-sense amp 310N and the P-sense amp 310P. In an initial state,the transistors, 301-304 of the N- and P-sense amps 310N, 310P areswitched off and no enabling signals are supplied to the NLAT* and ACTmodes. The sense operation of sense amplifier 300 is a two phasedoperation in which the N-sense amp 310N is triggered before the P-senseamp 310P.

[0033] The N-sense amp 310N is triggered by bringing the potential atnode NLAT* towards ground potential. As the potential difference betweennode NLAT* and the bit lines 106A and 106 a′ approach the thresholdpotential of NMOS transistors 301, 302, the transistor with the gatecoupled to the higher voltage bit line begins to conduct. This causesthe lower voltage bit line to discharge towards the voltage of the NLAT*node. Thus, when node NIAT* reaches ground potential, the lower voltagebit line will also reach ground potential. The other NMOS transistornever conducts since its gate is coupled to the low voltage digit linebeing discharged towards ground.

[0034] The P-sense amp 310P is triggered (after the N-sense amp 310N hasbeen triggered) by bringing the potential at node ACT from groundtowards Vdd. As the potential of the lower voltage bit line approachesground (caused by the earlier triggering of the N-sense amp 310N), thePMOS transistor with its gate coupled to the lower potential bit linewill begin to conduct. This causes the initially higher potential bitline to be charged to a potential Vdd. After both the N- and P-senseamps 310N, 310P have been triggered, the higher voltage bit line has itspotential elevated to Vdd while the lower potential bit line has itpotential reduced to ground. Thus, the process of triggering both senseamps 310N, 310P amplifies the potential difference created by the accessoperation to a level suitable for use in digital circuits. Inparticular, the bit line 106 a associated with the memory cell 400 abeing read is driven to ground if the memory cell 400 a stored a chargecorresponding to a binary 0, or to Vdd if the memory cell 400 a stored acharge corresponding to a binary 1, thereby permitting a compactor (ordifferential amplifier) 350 a coupled to bit lines 106 a, 106 a′ tooutput a binary 0 or 1 consistent with the data stored in the cell 400 aon signal line 351.

[0035] Returning to FIGS. 4A and 4B, at time period T2, the N-senseamplifier 310N is activated (start of step S3). As previously noted,activating the N-sense amplifier causes the bit line (one of 406 a and406 a′) having the lower potential to be pulled with the NIAT signaltoward ground. In the exemplary embodiment, T2 is approximately 30nanosecond after the world line activation at T1. However, it should benoted that the timing of T2 may be varied without departing from spiritor scope of the invention.

[0036] At time period T3, the P-sense amplifier 310P is activated. Aspreviously noted, activating the P-sense amplifier causes the bit line(one of 406 a and 406 a′) having the higher potential to be pulledtowards Vdd. In the exemplary embodiment, T3 is approximately 35nanosecond after T1 (end of step S3). However, it should be noted thatthe timing of T4 may also be varied without departing from spirit orscope of the invention.

[0037] As shown in both FIGS. 4A and 4B at time T4 after both the N- andP-sense amplifies have been fired, one of the bit lines 406 a, 406 a′ isat ground and the other is at Vdd, depending on the resistance of cell400 a. Since one bit line coupled to sense amplifier 300 a is now atground potential while the other bit line is now at Vdd potential, acomparator (or differential amplifier) 350 can be used to output a valuecorresponding to the contents of the cell 400 a on signal line 351 a.

[0038] Next, FIG. 7 shows a voltage chart describing a re-write/refreshoperation for a read memory cell 400 a in accordance with an exemplaryembodiment of the invention. In this exemplary process flow, thefollowing parameters of the programmable conductor memory cells arepresumed: i) that the voltage across an element 402 required to writefrom a high resistance state to a low resistance state is 0.25V; and ii)that the voltage across elements 402 required to write from a lowresistance state to a high resistance state is −0.25V. It should bereadily apparent that alternative voltages may be used depending on thematerial composition, size and construction of the programmableconductor memory element 402.

[0039] Referring back to FIG. 6 after the read operation occurs, thewrite process begins at step S4 by first writing to the opposite datathat was sensed at step S3. Hence, if memory cell 400 a is to be writtenback to a “1,” state (from step S3) then the cell is first written tothe opposite or complement data (i.e., “0” state), as shown in step S4,and then written back to the correct read state (i.e., “1”), as shown instep S5. Alternatively, if memory cell 400 a is to be written back to a“0” state, then the cell is first written to the opposite data state(i.e., “1”) and then written back to the correct data state (i.e., “0”).

[0040] As shown in FIG. 7, and assuming Vdd=2.5 volts and Vdd/2=1.25volts, to write a programmable memory element 402 a to a low resistancestate requires a voltage of greater than or equal to +0.25 across thememory element 402 a. Thus, if the bit line voltage V1 is set to Vdd andthe access transistor 401 a is turned on to 2.5 volts, and if there isapproximately a V2=1 volt drop or less across the transistor, thevoltage V3 drop across the cell is +0.25 or higher which is sufficientto program it to a low resistance state.

[0041] If memory element 402 a is to be written to a high resistancestate, then the voltage across the memory element 402 a must be lessthan −0.25 volts. To obtain this the bit line voltage V1 can be set toground and the word line is activated. If the voltage drop V2 across thetransistor is again 1 volt or less, then the voltage drop across thememory element V2=−0.25, or less which is sufficient to program a memoryelement to a high resistance state.

[0042] Thus, by controlling the voltage on the bit line and word linefollowing the memory element read operation, a read memory element canbe set to a particular logic state. In the invention, once a memoryelement 402 a is read, it is refreshed by first writing the logic stateof the memory element to its complementary state and then writing itback again to its original logic state. Thus, if a read memory element402 a holds a high resistance state e.g. logic “1,” it is refreshed byfirst writing it to a low resistance state, e.g. logic “0.” And thenwriting it again to a high resistance state e.g. logic “1.”

[0043]FIG. 8 illustrates one exemplary refresh circuit which can be usedto refresh a read memory element. FIG. 8 illustrates a portion of theFIG. 3 memory structure including the memory cell 400 a including accesstransistor 401 a and memory element 402 a. Also shown is a bit linecharge circuit 911 which is used following a read operation to set bitline 406 a to voltage of either Vdd or ground.

[0044]FIG. 8 also illustrates a refresh signal generating circuit 921for generating the refresh signal applied to control the bit line chargecircuit 911. The refresh signal generating circuit 921 includes aninverter 903 which receives an output signal from bit line 406 a and adelay circuit 905.

[0045] The operation of the refresh circuit illustrated in FIG. 8 willnow be explained with reference to the timing diagram shown in FIGS. 4Aand 4B. The timing diagram of FIG. 4A shows the bit line 406 a as havinga value of Vdd after a read operation at time T4. Because the voltage onbit line 406 a is Vdd and the word line 405 a has been turned to 2.5V,the high resistance state of memory element 402 a is read, and the Vddon the bit line will cause the memory element to see +0.25 volts acrossit which will automatically program it to a low resistance state beforetime T4 when a read operation is completed. In order to reprogram thememory element back to a high resistance state, the bit line 406 a isbrought to ground by an inversion of the Vdd value in inverter 903 andapplication of the inverted bit line 406 a voltage as an input to bitline charge circuit 911 and drop the bit line voltage to ground at timeT5. Then, if word line 405 a is then enabled, as shown at time T6 inFIG. 4A, there will be a negative 0.25 volt across the memory element402 a which is sufficient to reprogram it back to a high resistancestate. Although FIG. 4A shows word line 405 a disabled at time T4 andre-enabled at time T6, it is also possible to keep word line 405 aenabled through the time period T4 to T7. Likewise, as shown in FIG. 4Bif the memory element 402 a originally held a low resistance value,prior to time T4, the ground voltage on the bit line 406 a produced bythe sense amplifier 300 a will produce a negative 0.25 volts across thememory element 402 a automatically programming it to a high resistancestate. The ground voltage on the bit line 406 a is converted to a Vddvoltage by inverter 903 and the delayed inverted signal is applied tobit line charge circuit 911 to apply a voltage of Vdd to bit line 406 aat T5. Then word line 405 a is enabled at T6 to program the memoryelement 402 a back to a low resistance state. Again, word line 405 a inFIG. 4B can also remain enabled during the period T4 to T7 if desired.

[0046] An enable transistor 917 controlled by an applied enable signalcan be used to enable or disable operation of the bit line chargecircuit 911 by a refresh operation.

[0047] The invention may also be used to only write a complementaryresistance value a back to a memory element after a read operation. Thiscan be implemented by eliminating the bit line charge circuit 911 andrefresh signal generating circuit 921 in FIG. 8 and only performing thefirst write operation illustrated in FIGS. 4A, 4B, that is, the refreshoperation up to time T4. In this embodiment, each time a read operationoccurs, the memory element is refreshed to its complementary logicstate. With this embodiment a flip flop 951 or other logic elementreceiving a delayed output from the sense amplifier 300 a, is used tocontrol an output data inverter 953 to enable/disable the inverter toensure a proper logic state is output from a memory element 402 a. Forexample, if the original logic value stored in memory element 402 a is a“1,” when this value is read out the first time the memory element 402 awill be refreshed with a logic “0” value. The “1” data output from senseamplifier will be sensed, after a delay by delay element 953, and flipflop 951 will be toggled from a “0” to a “1” value. The next time memoryelement 402 a is read, the stored logic value of “0” needs to be outputas a “1” and flip flop 951 which now holds a “1” value enables inverter953 so that the read “0” value from memory element 402 is correctlyoutput as a logic “1” value. The output of the sense amplifier is againdelayed and used to toggle flip flop 951 back to a “0” state which willnot enable inverter 953 on a subsequent read operation. Since the “0”read by sense amplifier 300 a will be rewritten in memory element 402 aas a “1,” the next time the memory element 402 a is read the stored “1”value will be read out and not inverted. This process repeats for eachread of memory element 402 a.

[0048]FIG. 9 is a block diagram of a processor based system 800, such asa computer system, containing a PCRAM semiconductor memory 802 asdescribed in connection with the other figures. The memory 802 may beconstituted as one or more memory chips or memory integrated circuitsmounted on a memory module, for example, a plug-in memory module such asa SIMM, DIMM, or other plug-in memory module. The processor based system800 includes a processor 801, a memory 802, a mass storage 803, and anI/O device 804, each coupled to a bus 805. While a single processor 801is illustrated, it should be understood that processor 801 could be anytype of processor and may include multiple processor and/or processorsand co-processors. Memory 802 is illustrated in FIG. 9 as having aplurality of PCRAM devise 500. However, memory 802 may only include asingle PCRAM device 500, or a larger plurality of PCRAM devices 500 thanillustrated, and/or may include additional forms of memories, such asnon-volatile memory or cache memories. While one mass storage 803 deviceis illustrated, the processor based system 800 may include a pluralityof mass storage devices, possibly of varying types such as, but notlimited to, floppy disks, CDROMs, CD-R, CD-RW, DVD, hard disks, and diskarrays. I/O device 804 may likewise comprise a plurality of I/O devicesof varying tepes, including, but not limited to keyboard, mouse, graphiccards, monitors, and network interfaces. Bus 805, while illustrated as asingle bus may comprise a plurality of buses and/or bridges, which maybe coupled to each other or bridged by other components. Some of thedevices 801-804 may be coupled to only a single bus 805, others may becoupled to a plurality of buses 805.

[0049] While the invention has been described in detail in connectionwith the exemplary embodiment, it should be understood that theinvention is not limited to the above disclosed embodiment. Rather, theinvention can be modified to incorporate any number of variations,alternations, substitutions, or equivalent arrangements not heretoforedescribed, but which are commensurate with the spirit and scope of theinvention. For example, many different types of equivalent circuits canbe used to supply the appropriate read and write voltages to the memorycells, e.g. 400 a. Accordingly, the invention is not limited by theforegoing description or drawings of specific exemplary embodiments, butis only limited by the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A memory device comprising, a programmableconductor memory element; an access circuit for coupling said memoryelement between an activated word line and an activated bit line duringa read operation; a sense amplifier coupled to said activated bit linefor sensing a first logical state of said memory element; and writingcircuitry for writing said memory element first to a complement sensedlogical state in response to said read operation and then writing saidmemory element back to said first logical state.
 2. The memory device ofclaim 1, wherein said first logical state is a first higher resistancestate and the complement logical state is a second lower resistancestate.
 3. The memory device of claim 1, wherein said first logical stateis a first lower resistance state and the complement logical state is asecond higher resistance state.
 4. The memory device of claim 1, furthercomprising a pre-charge circuit for pre-charging the activated bit lineand a reference bit line prior to a sensing operation of said senseamplifier, wherein said activated bit line and said reference bit lineare coupled to the sense amplifier.
 5. The memory device of claim 1,wherein said writing circuitry further comprises a bit line chargecircuit for setting a voltage for said bit line.
 6. The memory device ofclaim 5, wherein said writing circuitry further comprises a refreshsignal generating circuit for generating a refresh signal applied tocontrol said bit line charge circuit.
 7. The memory device of claim 1,wherein said access circuit comprises a transistor.
 8. The memory deviceof claim 1, wherein said programmable conductor memory element comprisesa chalcogenide glass.
 9. The memory device of claim 6, wherein saidchalcogenide glass comprises a Ge:Se: glass composition which is dopedwith silver.
 10. A programmable conductor memory circuit comprising: aprogrammable conductor memory element; an access device for enabling aread and write access to said memory element; and a circuit foroperating said access device to read a logical value stored in saidmemory element and then writing a complementary logic value into saidmemory element.
 11. The memory circuit of claim 10, further comprising:a bit line and a sense amplifier coupled to said bit line and to areference voltage line during at least a read access of said memoryelement, said sense amplifier sensing a logic state of said memoryelement and setting said bit line at a predetermined voltage dependingon a sensed logic state of said memory element; and said circuitenabling said access device to couple said memory element between avoltage source and said bit line for a read operation and for enablingsaid access device to couple said memory element between said voltagesource and said bit line after said sense amplifier sets said bit lineat said predetermined voltage.
 12. The memory of claim 10, furthercomprising a logic circuitry for keeping track during a read operationwhether the read logical value should be output as read or invertedbefore being output.
 13. The memory of claim 12, wherein said logiccircuitry further comprises a flip flop to control an output datainverter to output a proper logic value.
 14. The memory device of claim11, further comprising a pre-charge circuit for pre-charging said bitline and said reference voltage line prior to a sensing operation ofsaid sense amplifier.
 15. The memory device of claim 10, wherein saidaccess device comprises a transistor.
 16. The memory device of claim 10,wherein said programmable conductor memory element comprises achalcogenide glass.
 17. The memory device of claim 16, wherein saidchalcogenide glass comprises a Ge:Se: glass composition which is dopedwith silver.
 18. A processor based system comprising, a processor; and amemory coupled to said processor, said memory comprising: a programmableconductor memory element; an access circuit for coupling said memoryelement between an activated word line and an activated bit line duringa read operation; a sense amplifier coupled to said activated bit linefor sensing a first logical state of said memory element; and writingcircuitry for writing said memory element first to a complement sensedlogical state in response to said read operation and then writing saidmemory element back to said first logical state.
 19. The system of claim18, wherein said first logical state is a first higher resistance stateand the complement logical state is a second lower resistance state. 20.The system of claim 18, wherein said first logical state is a firstlower resistance state and the complement logical state is a secondhigher resistance state.
 21. The system of claim 18, further comprisinga pre-charge circuit for pre-charging the activated bit line and areference bit line prior to a sensing operation of said sense amplifier,wherein said activated bit line and said reference bit line are coupledto the sense amplifier.
 22. The system of claim 18, wherein said writingcircuitry further comprises a bit line charge circuit for setting avoltage for said bit line.
 23. The system of claim 22, wherein saidwriting circuitry further comprises a refresh signal generating circuitfor generating a refresh signal applied to control said bit line chargecircuit.
 24. The system of claim 18, wherein said access circuitcomprises a transistor.
 25. The system of claim 18, wherein saidprogrammable conductor memory element comprises a chalcogenide glass.26. The system of claim 25, wherein said chalcogenide glass comprises aGe:Se: glass composition which is doped with silver.
 27. A processorbased system comprising, a processor; and a memory coupled to saidprocessor, said memory comprising: a programmable conductor memoryelement; an access device for enabling a read and write access to saidmemory element; and a circuit for operating said access element to reada logical value stored in said memory device and then writing acomplementary logic value into said memory element.
 28. The system ofclaim 27, further comprising: a bit line and a sense amplifier coupledto said bit line and to a reference voltage line during at least a readaccess of said memory element, said sense amplifier sensing a logicstate of said memory element and setting said bit line at apredetermined voltage depending on a sensed logic state of said memoryelement; and said circuit enabling said access device to couple saidmemory element between a voltage source and said bit line for a readoperation and for enabling said access device to couple said memoryelement between said voltage source and said bit line after said senseamplifier sets said bit line at said predetermined voltage.
 29. Thesystem of claim 27, further comprising a logic circuitry for keepingtrack during said read operation whether the read logical value shouldbe output as read or inverted before being output.
 30. The system ofclaim 29, wherein said logic circuitry further comprises a flip flop tocontrol an output data inverter to output a proper logic value.
 31. Thesystem of claim 27, further comprising a pre-charge circuit forpre-charging said bit line and said reference voltage line prior to asensing operation of said sense amplifier.
 32. The system of claim 27,wherein said access device comprises a transistor.
 33. The system ofclaim 27, wherein said programmable conductor memory element comprises achalcogenide glass.
 34. The system of claim 33, wherein saidchalcogenide glass comprises a Ge:Se: glass composition which is dopedwith silver.
 35. A method for operating a programmable conductor randomaccess memory element, said method comprising: sensing a logical valuestored in said memory element; writing a logical value which is thecomplement of the read logical value to said memory element in responseto said act of reading.
 36. The method of claim 35, further comprisingthe act of writing said sensed logical value after writing saidcomplement logical value.
 37. The method of claim 35, wherein said readlogical value is stated in said memory element as a resistance value.38. The method of claim 35, wherein said programmable conductor memorycell comprises a chalcogenide glass.
 39. The method of claim 38, whereinsaid chalcogenide glass comprises a Ge:Se: glass composition which isdoped with silver.
 40. A method for writing data to a programmableconductor random access memory element, said method comprising:pre-charging a first bit line coupled to the programmable conductorrandom access memory element to a first voltage value; pre-charging asecond bit line to a second voltage value, said first value beingdifferent from said second value; enabling an access transistor tocouple the programmable conductor memory element to said first bit line;sensing voltage on said first bit line and said second bit line todetermine a first logical state of said programmable conductor memoryelement; and writing a second logical state complementary to said firstlogical state to said memory element after said first logical state isdetermined.
 41. The method of claim 40, wherein said programmableconductor memory element comprises a chalcogenide glass.
 42. The methodof claim 41, wherein said chalcogenide glass comprises a Ge:Se: glasscomposition which is doped with silver.